INVESTIGATION OF FLIP-FLOP PERFORMANCE ON DIFFERENT TYPE AND ARCHITECTURE IN SHIFT REGISTER WITH PARALLEL LOAD APPLICATIONS
Abstract: Register is one of
the computer components that have a key role in computer organisation. Every
computer contains millions of registers that are manifested by flip-flop. This
research focuses on the investigation of flip-flop performance based on its
type (D, T, S-R, and J-K) and architecture (structural, behavioural, and
hybrid). Each type of flip-flop on each architecture would be tested in
different bit of shift register with parallel load applications. The experiment
criteria that will be assessed are power consumption, resources required,
memory required, latency, and efficiency. Based on the experiment, it could be
shown that D flip-flop and hybrid architecture showed the best performance in
required memory, latency, power consumption, and efficiency. In addition, the
experiment results showed that the greater the register number, the less efficient
the system would be.
Author: Dwi Purnomo, Machmud
Roby Alhamidi, Ari Wibisono, Muhammad Iqbal Tawakal
Journal Code: jptkomputergg150012
