AN OPTIMIZED SQUARE ROOT ALGORITHM FOR IMPLEMENTATION IN FPGA HARDWARE
Abstract: This paper presents
an optimized digit-by-digit calculation method to solve complicated square root
calculation in hardware, as a proposed simple algorithm for implementation in
field programmable gate array (FPGA). The main principle of proposed method is
two-bit shifting and subtracting-multiplexing operations, in order to achieve a
simpler implementation and faster calculation. The proposed algorithm has
conducted to implement FPGA based unsigned 32-bit and 64-bit binary square root
successfully. The results have shown that proposed method is most efficient of
hardware resource compare to other methods. In addition, the strategy can be
expanded to larger number easily.
Penulis: Tole Sutikno
Kode Jurnal: jptkomputerdd100020
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