Effect of Underlap and Its Soft Error Performance in 30 nm Junctionless Based 6T- SRAM Cell
Abstract: As CMOS device is
scaling down significantly, the sensitivity of Integrated Circuits (ICs) to
Single Event Upset (SEU) radiation increases. The Sensitivity of ICs to soft
errors emerge as reliability threatwhich motivates significant interest in the
development of various techniques both at the device and circuit level for SEU
hardness in SRAM memories. To facilitate the scaling the concept of underlap
GateSource/Drain (G-S/D) was suggested in the literature. Lun is one of the
sensitive geometrical parameter considered to differ from 1 nm to 5 nm in a SEU
radiating environment. The effect of Gate-Source/Drain underlap (Lun) on soft
error performance in 30 nm Junctionless Transistor (JLT) based on 6T-SRAM cellhas
been examined through extensive mixed mode-device and circuit simulations using
TCAD. The critical dose observed in JLT based 6T-SRAM with Lun ranging from 1
nm to 5 nm to flip the cell is given by Linear Energy Transfer (LET) between
0.05 to 0.06 pC/µm. The simulation result analyzes electrical and SEU radiation
parameters to study its impact on JLT based 6T-SRAM cell.
Author: P Chitra, V N
Ramakrishnan
Journal Code: jptkomputergg150066
