FPGA Implementation of Low-Area Square Root Calculator
Abstract: Square root is one
of the mathematical operations which are widely used in digital signal
processing. Its implementation on hardware such as FPGA will provide several
advantages compare to the performance offered in software. There are several
algorithms which can be utilized for this calculation, but they are difficult
to be implemented in FPGA. This paper presents a model of FPGA based square
root calculator, which requires very low resources usage, thus occupying very
low area of FPGA. The model is designed to suit the needs of medium-speed and
low-speed applications which don’t need very high processing speed, while
optimizing the number of resources utilized.The modified non-restoring
algorithm is used in this design to compute the square root. The design is
coded in RTL VHDL, and implemented in Altera DE2-board for hardware validation.
The implementation produced very precise square root calculation, with low
latency computation and low area consumption, for various input data width
tested.
Author: Aiman Zakwan Jidin,
Tole Sutikno
Journal Code: jptkomputergg150137
