HARDWARE-RESOURCE SAVING FOR REALIZATION OF SPACE VECTOR PWM BASED ON FPGA USING BUS-CLAMPING TECHNIQUE
Abstract: The space vector
pulse width modulation (SV-PWM) is more suitable and can increase the
obtainable DC voltage utilization ratio very much compared to others PWM.
Moreover, the modulation can obtain a better voltage total harmonic distortion
(THD) factor. But until now, no studies that concern at hardware resources
saving to realize SV-PWM based on FPGA. This paper proposes a new technique to
realize SV-PWM based on FPGA. In order to get hardware resource saving, a
simple technique to judge sectors, to calculate the firing pulses and to
generate SV-PWM waveform without calculation of trigonometric function using
bus-clamping technique is proposed. The technique has been implemented
successfully based on APEX20KE FPGA to drive three phase induction machine 1.5
kW with low ripples in current and voltage, and has been shown that the
proposed SVM method required the most minimum hardware resources compared to
others research.
Penulis: Tole Sutikno
Kode Jurnal: jptkomputerdd090040
