OPTIMALISASI DESAIN KENDALI KECEPATAN PUTAR MOTOR INDUKSI TIGA FASA BERBASIS FPGA
Abstract: FPGA based the
problem of implementation of PWM signal generating system is solution of
transformation to digital gate logic space. These stages are done with
sampling, quantizing and coding. Best resolution of sampling and carrier
frequency, so result of PWM generating is better, but it required most digital
gate. Aim of this research is optimization of last research adjustable speed
drive of three-phase induction motor; with improve resolution of sampling and
carrier frequency, and minimalization of digital gate used with Quine Mc
Cluskey method. Result of this research indicate that the design of optimalized
SPWM generating signal can be realized in hardwared-logic in ACEXIK FPGA to
drive inverter as speed controller turn around the three phase induction motor,
with requiring 1629 logic cell. Adjustable motor speed designed can be done by
through setting make a modulation index and frequency. At this research, system
have been tested at setting frequency 3-50 Hz with the variation of modulation
index, and can adjustable three phase induction motor speed in range
117-1468 rpm.
Penulis: Tole Sutikno
Kode Jurnal: jptkomputerdd080034
