High throughput FPGA implementation of Advanced Encryption Standard algorithm
Abstract: Owing to the
worldwide increase of electronic communications and transactions, security and encryption
speed have become essential elements of all systems and applications. Advanced
Encryption Standard (AES) is one of the most widely secure and used symmetric
encryption algorithms today. In this paper, we present high throughput
full-pipelining implementation of AES algorithm, using the least amount of
possible hardware. Substitution box (S-box) is the only non-linear step in this
algorithm. It is the most complicated and costly part of the system.
Consideration on high delay and hardware cost required for this transformation,
we proposed pipelined S-box implementation by using composite field, to deal
with the critical path and the occupied memory. In addition, efficient key
expansion architecture suitable for our proposed AES design is also presented.
The implementation has been successfully done by Virtex-5 XC5VLX85 and Virtex-6
XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE 14.7.
Our high throughput AES design achieves a data encryption rate of 108.69 Gbps
and uses only 6361 slices. Compared to the best previous works, this
implementation improves data throughput by 5.6% and reduces the occupied memory
by 77.69%.
Author: Soufiane Oukili, Seddik
Bri
Journal Code: jptkomputergg170162
