Implementation and Analysis of Reversible logic Based Arithmetic Logic Unit
Abstract: There is a
tremendous growth in fabrication from small scale integration (SSI) to giant
scale integration (GSI). It however raises a question of sustainability of
Moore's law due to almost intolerable levels of power consumption. Researchers
have invented a lot of methods to reduce power consumption and recent
technologies are switching to reversible logic. Reversible logic has various
applications in fields of computer graphics, optical information processing,
quantum computing, DNA computing, ultra low power CMOS design and
communication. ALU is considered to be the basic building block of a CPU in the
computing environment and portability in computing system highly demands
reversible logic based ALU. Modern processors usually have a word length of 32
or 64 bits. Divide and conquer approach principle cascades n number of 1 bit
ALU to implement n bit ALU. Several researchers have proposed 1-bit ALU design
using various reversible logic gates. This paper aims at categorizing various
ways ofimplementation in VHDL using Xilinx ISE design suit 14.2 tool and
comparative analysis of existing 1 bit ALU designs in terms of optimization
metrics like power consumption, number of gates, number of constant inputs,
number of garbage outputs and quantum cost .ALU realized using carry save adder
block is found to be most optimum design in terms of gate count and quantum
cost.
Author: Shaveta Thakral
Journal Code: jptkomputergg160286
