Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation
Abstract: Low Density Parity
Check Code (LDPC) is a kind of linear block codes based on sparse check matrix.
As a kind of channel coding, whose error performance approach Shannon limits,
it has better error correction capability, more flexible structure and lower
decoding complexity. Currently most of the LDPC code researches are on the
premise of the AWGN channel and BSC channel, which mainly in the range of the
binary LDPC codes. According to the above problem, this paper analyzes the
various decoding performance of non-binary LDPC codes in Rayleigh channel, and
realizes a non-binary LDPC decoder in Rayleigh channel through the FPGA design.
The paper begins with an overall discussion of issues surrounding the use of
non-binary LDPC codes. And then the bit-error-rate (BER) performances of different
non-binary LDPC codes decoding algorithm are compared on the independent
Rayleigh fadingchannel. Finally, this decoder design is implemented based on
5CSEMA5F31C6 FPGA (devised by Altera Company) to illustrate the concepts
discussed in the paper.
Author: Zhongxun Wang, Juan
Hui
Journal Code: jptkomputergg160029
