Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture
Abstract; In essence,
Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed
as a design solution to System-on-Chip (SoC). The routing algorithm, topology
and switching technique are significant because of the most influential effect
on the overall performance of Network-onChip (NoC). Designing of large scale
topology alongside the support of deadlock free, low latency, high throughput
and low power consumption is notably challenging in particular with expanding
network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology
schemes for Network-on-Chip to minimize the latency by decrease the node
diameter from the source node to destination node. Correspondingly, we compare
in differences on the performance of mesh, full-mesh, torus and ring topologies
with XX-Torus and XX-Ring topologies in term of latency. Results show that
XX-Ringoutperforms the conventional topologies in term of latency. XX-Ring
decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over
the mesh, fully-mesh, torus, XX-torus, and Ringtopologies.
Author: Ng Yen Phing
Journal Code: jptkomputergg170071
